(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming a shallow trench isolation in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Shallow trench isolation (STI) is an important enabling technology for processes with device sizes 0.25 microns and below. STI technology makes possible the formation of active area isolations with reduced surface area and flatter topology than with local oxidation of silicon (LOCOS) schemes. Polishing and etch stop layers must be completely removed after the formation of the STI. It is difficult to remove these layers without creating defects in the trench oxide of the STI. The present invention addresses this problem.
Referring now to FIG. 1, a cross-section of a partially completed prior art integrated circuit device is shown. A shallow trench isolation will be formed using a prior art method. A semiconductor substrate 10 is shown. A pad oxide layer 14 is formed overlying the semiconductor substrate 10. A silicon nitride layer 18 is formed overlying the pad oxide layer 14. The silicon nitride layer 18, pad oxide layer 14, and the semiconductor substrate 10 are patterned to form the trench for an STI. A trench oxide layer 22 is deposited overlying the silicon nitride layer 18 and filling the trench.
Referring now to FIG. 2, the trench oxide layer 22 is polished down. The silicon nitride layer 18 acts as a polishing stop.
Referring now to FIG. 3, the silicon nitride layer 18 and the pad oxide layer 14 are etched away. This etching away typically involves a wet etch using a chemistry such as diluted hydrofluoric acid (HF). This etching away step can cause a grooving 26 of the trench oxide layer 22 along the top corners of the STI. The grooves 26 can cause excessive junction leakage for active devices fabricated adjacent to the grooved STI. In addition, MOS devices fabricated adjacent to the grooved STI can experience gate oxide thinning at the boundary that can reduce the gate breakdown voltage.
Several prior art approaches disclose methods to form shallow trench isolations. U.S. Pat. No. 5,804,493 to Juang et al teaches a process to form local oxidation of silicon (LOCOS). A stack is formed comprising silicon nitride over polysilicon over pad oxide over the semiconductor substrate. The silicon nitride and polysilicon are etched to form masks overlying planned active areas. Field oxide is formed by thermal oxidation of the semiconductor substrate. The silicon nitride and polysilicon layers are stripped to complete the LOCOS. U.S. Pat. No. 5,811,345 to Yu et al discloses a method to form STI. A stack is formed comprising polysilicon over nitride over pad oxide over a semiconductor substrate. A trench is etched. Ozone TEOS is deposited to fill the trench. An HF dip is performed to planarize the trench oxide. A plasma etch removes the trench oxide down to the polysilicon layer to complete the STI. U.S. Pat. No. 5,837,612 to Ajuria et al discloses a method to form STI. A polysilicon layer is deposited over an oxide layer that overlies the semiconductor substrate. A thermal oxidation is performed to form an oxide layer over the polysilicon layer and to line the trench. An oxide fill layer is deposited to fill the trench. A reverse mask is used to etch down the oxide fill outside the trench. A CMP is performed to polish down the oxide fill to the top of the oxide over the polysilicon. The polysilicon layer is then etched away. U.S. Pat. No. 4,671,970 to Keiser et al teaches a method to form STI. Trenches are etched into the semiconductor substrate. A stack of polysilicon overlying silicon nitride overlying silicon dioxide is formed overlying the substrate and inside the trenches. A CVD oxide is deposited to fill the trenches. The oxide is etched away excepting corner fillets in the lower corners of the trenches. A second oxide is grown by thermal process to fill the trenches. U.S. Pat. No. 5,923,991 to Bronner et al discloses a method to prevent divot formation in an STI process. A silicon nitride layer and silicon nitride spacers are used. U.S. Pat. No. 5,895,254 to Huang et al teaches a method to form STI. Silicon nitride is formed over pad oxide over the substrate. An opening is etched through the silicon nitride. A trench is etched into the substrate using the silicon nitride as a mask. A liner oxide is formed. A trench oxide is formed and polished down. The silicon nitride is etched away. Spacers are formed in the pad oxide at the trench edges. The pad oxide is removed to complete the STI.